1. Field of the Invention
The present invention relates to a thin film transistor (to be referred to as "TFT" hereinafter) and a liquid crystal display device (to be referred to as "LCD" hereinafter) using it.
2. Description of the Related Art
Recently, an LCD is widely used for a wordprocessor, a personal computer, a projection type TV, a small TV or the like. Among the LCDs for these devices, the development of an active matrix type of LCD using a TFT is expected which has less crosstalk and a contrast ratio of more than 100 and in which image quality as good as a CRT can be obtained in moving picture display. The problems of the LCD to be improved from now are the further improvement of image quality, the increase of the number of pixels, and the expansion of size.
For solving these problems it is efficient to improve the performance of TFT. Specifically, in the self-alignment type of TFT, great development is expected to be achieved. The feature of the self-alignment type of TFT is in that a large size of display can be formed uniformly with a low mask alignment precision and the overlapping of a gate and a source or drain can be made small so that a capacitance between electrodes can be also made small. Further, since channel length can be made short, it is possible to increase the turn-on current of TFT.
FIG. 9 is a cross sectional diagram showing a self-alignment type of TFT disclosed in Japanese Patent Laid-Open Application No. Hei-1-(1989)-183854.
As shown in FIG. 9, a gate electrode 2 is formed on a glass substrate 1, and a gate insulating layer 3 is deposited thereon. Further, an amorphous silicon (to be referred to as "a-Si" hereinafter) layer 4 is formed at the position corresponding to the gate electrode 2 thereon as a channel region. An n.sup.+ -type a-Si layer 7 is provided at both sides of the a-Si layer 4. A silicide layer 9 obtained by reacting metal and silicon is formed on the n.sup.+ -type a-Si layer 7 , on which source and drain electrodes 10 are formed. A channel protecting layer 6 is formed on the a-Si layer 4.
In the TFT as described above, in order to increase the turn-on current it is effective to shorten the channel length L. This is because the turn-on current increases in inverse proportional to the channel length L if a mobility of carriers is constant at the channel. However, the inventors made it sure from experiment that the actual turn-on current was smaller than a predicted value. Decrease of the mobility makes drive capability of TFT small, so that high speed operation becomes difficult.
As a result of analysis of the cause of the above phenomena by the inventors, it could be found that the turn-on current decreased due to a parasitic resistance in the n.sup.+ -type a-Si layer 7 of the source and drain regions. Also, it could be found that a contact resistance between the n.sup.+ -type a-Si layer 7 of the source and drain regions and the silicide layer 9 is specifically high among the parasitic resistance.